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Project 42: Hybrid CMOS-Spintronics/MEMS Integrated Circuit design

Suitable Majors

Electrical Engineering

Research Area

Microelectronics, Spinelectronics, MEMS

Internship Description

To design ultra-low power memory and logic circuits using beyond-CMOS technologies.​
Methodology: ​The works includes modelling using standard tools (verilogA and OOMMF), design and simulation (Cadence and Synopsis tools) and fabrication (tape-in)​ 

Prerequisites

Familiarity with circuit design tools (Cadence tools) andundergraduate level electromagnetics

Deliverables/Expectations

An operational CMOS-spin/MEMS logic or NVM, fully integrated

Other Comments

​Internship dates: 19 May to 26 July or 23 June to 29 August or 7 July to 14 September​

Division

Computer, Electrical and Mathematical Sciences and Engineering

Faculty Name

Hossein Fariborzi